Computer having floating point multiplication



Feb. 14, 1967 15 Sheets-Sheet l Original Filed Ooi..

INVENTR. THEODORE M. HERTZ BYC( 1 ATTORNEY T. M. HER-rz 3,304,417

COMPUTER HAVING FLOATING POINT MULTIPLICATION Feb. 14, 1967l 15 Sheets-Sheet Original Filed OCT.. l, 1962 8302 u md u o md msgs mw mmPm-Omm mi/LW ATTORNEY Feb. 14, 19,67 3,304,417

COMPUTER HAVING FLQATING POINT MULTIPLICATION T. M. HERTZ 15 Sheets-Sheet 5 ADDERSUBTRACTOR CIRCUIT OPERATION COD E SELECTION Orlglnal Flled Oct EMISIERW V... l o REGISTER i 6 F F l INPUTIKITOBI C REGISTER TIMING AND FLIP FLOPS GFF:

TO CONTROL READ AND WRITE MEMORY MATRICES INDICATOR AND CONTROL Typgwnrrgn INVENTOR THEoDoRl-z M. HERTz FROM FROM K9 TO II INPUT OUTPUT SELECTOR FIG. 3

ATTORNEY Feb. 14, 1967 l5 Sheets-Sheet 4 Originall Filed Oct. l, 1962 INVENTOR. THEODORE M. HERTZ ATTORNEY Feb. 14, 1967 T. M. HERTZ 3,304,417

COMPUTER HAVING FLOATING POINT-MULTIPLICATION Original Filed Oct. l, 1962 15 Sheets-Sheet 5 ICH Input number of characters from device specified Ol OCH Output number of characters from device specified 02 ALS Shift number in A register left by amount specified 02 .2 ASV Same as 02 with overflow indication of l lost 02.4 ASC Same as 02 with normalizing optional termination O3 ARS Shift A register right by amount specified 05 STR Store number in R register in address speci fied l0 TIX Transfer to new location count if index O, decrement ll TNZ Transfer if number in A register is not equal to zero l2 SAP Set sign of A register positive 12.4 SAN Set sign of A register negative 13 CSA Change sign of the A register 15 TLB Transfer i'f the least significant bit of A is a one 16 CAZ Clear A register to plus zero 16.4 CMZ Clear A register to minus zero 17 CMP One's complement A register bits, including sign 17.4 RND Round A register number if most significant R bit is l 25.1 STI Store index in right hand address portion specified 31.1 LDI Read index from right hand portion of address to G41 CMG Compare, set Jo true for B A, false for B A 35.4 CME Compare, set Jo true for B A or B A, false for B A 3G CLS Clear A register and subtract addressed operand 37 CLA Clear A register and add addressed operand thereto 40 CTL Copy from address specified to L loop to end of loop 41 CTV Copy from address specified to V loop to end of loop 42 LLS Long left shift A and R registers by amount specified 42.2 LSV Same as 42 with overflow for loss of a 1 by shift 42,4 LSC Same as 42 with normalizing optional termination 43 LRS Long right shift of A and R registers 44 CFL Copy from L loop to Main memory starting at address 45 STO Store number in A register in address specified TZE Transfer if number in A register is zero 5l TRA Transfer unconditionally 52 TOV Transfer on overflow (no halt if overflow) 53 TMI Transfer if A register sign is negative 54 NOP No operation 55 TPL Transfer if A register sign is positive 5G XAR Interchange A and R registers 57 CAR Copy A register into the R register, clear A 63 MPY Multiply A number by operand in address specified 65 STA Store address in A register in address specified 66 DIV Divide A number by operand in address specified 70 EXT Logical multiplication of A number by operand specified 7l HTR Halt and transfer unconditionally 72 SUB Subtract operand specified from A register number 73 ADD Add operand specified to A register number 76 RCS Clear and subtract (Copy A to R) 77 RCA Clear and Add (Copy A to R) 23 EMP Floating Multiply 26 FDV Floating Divide 74 FSB Floating Subtract 75 FAD Floating Add Assume overflow was off; if overflow was on initially then if B A 0, do

nothing; if B A O, reverse Jo INVENTOR. FIG. 5 THEODORE M. HERTZ mofw ATTORNEY Feb. 14, 1967 T. M. HERT-z 3,304,417

COMPUTER HAVING FLOATING POINT MULTIPLICATION Original Filed Oct. l, 1962 15 Sheets-Sheet 6 inno (iwi) FIDATING MULTIPLY IVDDE l. Floting multiply operation wie 23 is Het in the D register 2. Multiplier operand initially in the A register Multiplicand operand copied into the B register 3. A count of "32" is set up in the G register lghl Do Kg D6' T20 (or T140) Ogbfl I! il li'. Fixed point multiply operation 63 is forced into IDDO mode at Th1 time 113e. Ml

E DWS' E D2 13a. D5 D14' D3' llllll FIG. 6

FIDATING MULTIPLY MODE l. If normalizing is required luz Fm Gl Kg T20 D3' od5 Nz'l'hl (Ileft shift) odu NzThl (Long left shift) ld3 NzThl (Long left shift) odl Nziul (long left shift) M li, Dh' D3 13a cli' 2. The most significant bit of the R register is copied into the least significant bit position of the A register SMM' Do' Il Il Il II 13a D5 Tho D6 (Reset initially) 3. Exponent is decremented by one for each bit left shift of the fraction operand during normalizing las lah oe3 Il ll Il N N N INVENTOR.

FIG 9 THEODORE M. HERTZ ATTORNEY Feb. 14, 1967 T. M. HERTz COMPUTER HAVING FLOATING POINT MULTIPLICATION 13 Sheets-Sheet 7 Original Filed Oct. l, 1962 MH EL@ .ma @n n um: QMIE .No u .2.5 d E: No n S @Q02 ANNEE UZHE ATTOR NEY Feb. 14, 1967 T. M. HERTZ COMPUTER HAVING FLOATING POINT MULTIPLICATION Original Filed Oct. l, 1962 ui (31 wT) FIDATING MULTIPLY MODE 15 Sheets-Sheet 8 Multiplicand operand multiplied by multiplier operand using fixed point multiplication lrl Orl Il Il Msr Precessing of* product of multiplication into the A register is stopped and fixed point addition in forced into the computer to terminate the multiply operation ldh Odli B register is recirculated to preserve contents (exponent) lbhO ObltO 'Il Il Exponent is copied from B register into the A register lalLO Bul Fm Dl D1 Do'12' oalio B141' Fm D1@ Dl Do' Product is checked for normalizing lcl Ocl lkc Okc Fm D3' Ka' T 33 (Not nominee.) E T1 (Normlizea) Il ll Il FIG. 8

INVENTOR.

THEODORE M. HERTZ ATTORNEY Feb. 14, 1967 13 Sheets-Sheet 9 Original Filed Oct. l, 1962 nowpmmgon man BMQMESQ aoHmmmund .Ho aodwngo pmwdomx .Hom oh www INVENTOR. THEODORE M HERTZ ATTORNEY Feb. 14, 1967 T.M. HERTZ COMPUTER HAVING FLOATING POINT MULTIPLICATION original Filed oct. 1, 1962 13 Sheecs--Sheefl lO ATTORNEY T. M. HERTZ 3,304,417

COMPUTER HAVING FLOATING POINT MULTIPLICATION Feb. 14, 1967 Original Filed Oct. l, 1962 y EPIIIIIN llllllllllllllllll Vl llllll |11|l||l ATTORNEY Feb. 14, 1967 Original Filed Oct. l, 1962 T. M. HERTZ COMPUTER HAVING FLOATING POINT MULTIPLICATION l5 Sheets-Sheet l2 THEODORE M. HERTZ ATTORNEY Feb. 14, 1967 T. M. HERTZ 3,304,417

COMPUTER HAVING FLOATING POINT MULTIPLICATION Original Filed Oct. l, 1962 13 Sheets-Sheet 1:5

CI FLIP FLOP FIG Low INDICAIxTEs TRUE 0R "l 0R+ INVENTOR. THEODORE M. HERTZ ATTORNEY United States Patent O 3,304,417 COMPUTER HAVING FLOATIN G POINT MULTIPLICATION Theodore M. Hertz, Whittier, Calif., assignor to North American Aviation, Inc. Continuation of application Ser. No. 227,365, Oct. 1, 1962. This application May 23, 1966, Ser. No. 552,341 8 Claims. (Cl. 23S-164) This application is a continuation of application Serial No. 227,365, filed October 1, 1962, and now abandoned.

This invention relates to electronic digital computers and more particularly to a `computer having floating point multiplication capabilities.

Prior art digital computers utilized fixed point arithmetic processes in executing computer operations. In performing fixed point arithmetic processes a computer assumes the binary point (analogous to a decimal point) to be between the sign of a number and the most significant digit of the number. Thus the number is considered to have an absolute value of less than one. As explained in patent application filed September 24, 1962, Serial No. 225,676, now abandoned, for a Computer Having Floating Point Addition 'and Floating Point Subtraction invented by me, in order to execute fixed point addition and subtraction operations, numbers =to be operated upon by a computer must first be appropriately scaled prior to computation in order to obtain meaningful results. The scaling of the numbers is accomplished prior to entering them in-to the computer or by shifting them through programming afterwards. Fixed point multiplication needs lto have numbers scale prior to performing computations with them. In multiplication, shifting of the result through programming is dfesirable in order to prevent loss of significant portions which should be retained for use in later computations. Particularly is it true Where after a multiplication operation has been performed, the product must be added or subtracted from or with other numbers, in which case scaling would first have to be done before the additional computation could be made.

In order to overcome the limitations above, a system -has been devised whereby numbers are automtically scaled inside the computer. This system is called herein a floating point arithmetic process. In the floating point format, `a word may be divided into a sign bit, a characteristic, and a mantissa. The characteristic is the exponent to which the base number 2 is raised. The mantissa is expressed as binary fraction, as a number less than one. In order to determine the numerical value indicated by the characteristic and mantissa, the base number 2 must first be raised to the value of the characteristic, and the results of that operation must then be multiplied by the fraction represented by the mantissa.

In fioating point multiplication the multiplier operand, designated by an exponent portion and a fraction portion, is initially transferred to a first register. The multiplicand is similarly transferred to a second register. A counter, or third register, is set up so that the multiplation operation can be terminated at a proper time. The multiplier fraction is transferred to a fourth register and the exponents of both the multiplier and multiplicland operands are added using ordinary fixed point adder logic. The sum of the exponents is then transferred to the second register so that the second register contains the multiplicand fraction and the combined or added exponents. Logic is included for terminating Ithe operation of either of the fraction is found to be zero.

When multiplying numbers having large exponents, an overfiow my occur. When multiplying two numbers having very small exponents, 'an exponent underfiow may occur. In both cases the overflow indicator is turned on :LEMAN Patented Feb. 14, 1967 fice to enable a programmer `to take appropriate correcting action.

The fractional portions of the operands in the registers are multiplied using fixed point multiplication logic. However the fractions are smaller in number of bits than the fixed point fractions by virtue of having had the portion of the number designated by the characteristic or exponent removed. At the end of the operation of multiplying the fractions, both the product and the exponent are transferred to the first register as a final product. If the result is not already in a normalized form, the fractional portion of the result is normalized by shifting it left and in order that the numerical value of the number remain the same, the new exponent is decremented by one for each bit the fractional portion is shifted left. The term de-normalization is the opposite of normalizing wherein the number is shifted left until a binary one appears in the most significant bit position of the register. In de-ncrmalization the numbers in a particular register are shifted right 'a predetermined number of bit positions, usually to align the operand in one register with an operand in another register or to avoid overfiow. The exponent portion of the numerical value involved is incremented by one for each bit of right shifting by addition. In either case, normalization or de-normalization, it can thus be seen that the value of the number remains the same.

It is therefore an object of this invention to provide a computer having simplified floating point multiplication.

It is still another object of this invention to provide an improved floating point multiplication operation in a computer.

Still another object of this invention is to provide serial floating point multiplication in an electronic computer.

A still further object of this invention is to provide floating point multiplication requiring no programmed normalization or de-normalization.

A further object of this invention is to provide an automatic normalizing and de-normalizing fioating point operation within a computer.

Another object of this invention is to provide a computer for handling floating point numbers in a more compact form.

A final object of this invention is to provide au entirely automatic floating point multiplication operation within a computer.

Still other objects and features of this invention will become apparent from the following drawings of which:

FIG. 1 i-s an illustration of a positive operand having an exponent portion and a fraction portion contained in an accumulator or A register within a computer;

FIG. 2 is an illustration of a negative operand having an exponent portion and a fraction portion contained in an accumulator or A register within a computer;

FIG. 3 is an illustration representing an entire electronic digital computer;

FIG. 4 is 'an illustration of an accumulator or A register;

FIG. 5 is an explanation of each of the operation codes;

FIG. 6 illustrates logic for InDo phase of the floating multiply operation;

FIIG, 7 illustrates logic for the U1 phase of the fioating multiply operation;

FIG. y8 illustrates logic for the Ui phase of the floating multiply operation;

FIG. 9 illustrates logic for the Nz phase of the fioating multiply operation;

FIG. 10 illustrates a block diagram of each step of the floating multiply operation;

FIG. 1l illustrate-s a portion of the logic mechanization for floating multiplication operations;

FIG. 12 illustrates a portion of t-he logic mechanization for floating multiplication operations;

FIG. 13 illustrates an actual electronic mechanization of the C1 flip iiop checking the most significant bit of the product for normalization; and

FIG. 14 is an illustration of a clock gated ytiip flop suitable for use in the device of the invention.

Referring now to FIG. 1, it is seen that iioating point information may be handled Iin ya computer in words each consistingr of 41 bits, the bits being numbered from right t-o left in order of increasing significance. The first bit is a synchronizin-g bit and is not utilized in computer operations. Bits 2 throu-gh 32 are utilized to indicate in binary form Athe fraction portion of the particular iioating point number being processed. The bits 33 through 40 are used to `indicate the exponents, that is the power to which the number 2 is raised. With such 8 bits, therefore, the number 2 may have any power from zero through 255, however, by introducing a bias of -128, the range is shifted by 128 to a range of -128 through 127 With bit 40 being utilized to indicate whether the exponent is plus or minus. For example, to represent `a num-ber having a negative exponent such as is the case of 2428, bit 40 is false (or zero) and bits 33 through 39 are 0000000. For 2 1, bits 40 through 33 are 01111111. For 2, bits 40 through 33 are 10000000. For 2+1 bits 40 through 33 are 10000001. For 2+2, bits 40 through 33 are 10000010. For 2+126, bits 40 through 33 are 11111110. For 2+127, bits 40 through 33 are 11111111.

Another way to describe the biasing effect .is to consider a register having a capability of counting from zero through 255. However, in order to establish a capability of counting below zero, there is included in the computer logic -gates t-o indicate a 01111111 for the exponent (-1, which stands for Zrl) and there are additional logic gates to cause the computer to count down 1 through 128) from 01111111 to 00000000. If bit 40 is minus then each bit changed to from l represents a greater numerical value (disregarding the sign). Thus -1 represented by 01111111 would be decremented to l128 represented by 00000000. If bit 40 is plus each decremented bit represents a decrease over a ran-ge of i127 through zero. Where the zero is relocated at the center of a registers counting range (the computer formerly being capable of counting from zero to 255, 4i.e., an 8 bit counter) allotting zero to one of the counts leaves a capability of counting up to +127 land down to -128.

In effect by dividing zer-o through 255 into two parts by appropriate logic gates, the register counts up from zero through 127 and down from -1 through 128. If bit 40 is minus, the register counts over the negative range. If bit 40 is positive, the register counts over the positive range.

A negative number is illustrated in FIG. 2. The exponent is expressed in 2s complement form which is obtained by subtracting the negative number from all zeros. The A40 bit is reversed during the multiplication operation so that the product will have the correct sign.

In all lioating point operations, logic control is utilized t-o insure that `all operations specified by the instructions are performed in the correct mode and in the proper sequence. Basic control elements in the computer are logic gates and tl'ip iiops operating in conjunction with control registers and other registers. The states of the flip flops define the logic control functions of mode designations, operation selection, loop and main memory selection, channel selection, and sector selection.

Flip iiops Il, I2, 'and I4 shown yin FIG. 3 are the primary elements controlling the computer through the various modes and in the transitions from one mode t-o another. Two other iiip iops designated as mode selection flip op Kc and memory write-read gating liip iiop D0 are also utilized as control elements. However, both Kc and D0 also perform other functions on a 4time sharing basis as do Ia number of other logic iiip tiops.

A D register comprised of flip liops D1 through D6, illustrated in FIG. 3, `defines the type of operation to be performed Iby the computer. The tiip flop settings are determined by the bit configuration and the operation code of each command. Outputs of the `flip liops then control the operation control gating matrix to define the type of operation specified.

The C register -is comprised of iiip tiops C1 through C6. The C register holds the channel address code which controls the gating of the write and read switching networks in the selection of a designated memory channel. Outputs of these iiip tiops enable the write or read head of a .selected channel after a desired sector has been located during the sector selection phase.

Sector selection is the procedure which determines the sector location of a designated command or operand in the mem-Ory. The Z register, the origin sector channel, and several associated iiip flops comprise the sector selection elements.

The control registers (Z and G) and -their associated logic circuits perform many of the control functions required in the location storage modification and execution of commands and in the handling of data. The A register is comprised of a write and read yamplifier and 39 bits circulating in the loop register channel. The Z register stores the command pair being executed. The G register, also comprised of a read and write amplifier and 39 bits circulating in the loop register channel, contains storage space for the location counter, index register. The G register is also used as a computation cycle counter.

The yarithmetic registers (A, B, and R) and their associated logic circuits perform the basic computer arithmetic functions of addition, subtraction, multiplication, and division. These registers also perfor-m many semi-arithmetic and control functions. In the execution of arithmetic commands the registers utilize two additional flip flops which, during the computations, form an adder-subtractor circuit.

The A or accumulator register shown -in FIG. 4 stores the information in six flip flops and in 35 bit positions in the loop-register channel. 4Utilized in all arithmetic computations, the A register accumulates all or a port-ion of the result of each computation.

The B register shown in FIG. 3 which is also referred to as the number register, utilizes three flip flops and 38 bit positions in the loop register channel. This is an intermediate storage register which is not directly addressable by the programmer. In most instances, the cornputer first stores a command or operand being read from or Written into memory in the B register, and then transfers the word to the intended locations as required. The remainder or R register shown also in FIG. 3, stores its contents in four iiip iiops and 37 bit positions n the loop register channel. (R42 and R43 iiip flops -are not an integral part of the register.) This register may be utilized as an extension of the A register in the execution of multiplication and division commands.

Principal computer elements involved in the execution of the arithmetic processes are the three arithmetic registers and ithe adder-subtractor circuit. The adder-subtractor circuit is comprised of a sum-difference ip flop S and a computation carry-borrow ip-liop Ka which operate in conjunction with the arithmetic registers to carry out the computations. The tiip flops S and Ka are illustrated in FIG. 3. Other computer elements such as the memory read/ write circuitry and the control registers also are utilized. However, these other elements perform associated functions which generally enter into virtually all of the computer operations.

The three arithmetic registers and the adder-subtractor circuit are the principal computation elements for both the fixed point and floating point arithmetic processes. However, additional iiip tiops and primary and secondary gates are necessary to control the lloating point processes. For example the computer utilizes the additional flip flop Fa during floating point addition -and subtraction functions `an-d Fm during floating point multiplication and division functions. Flip flop Ec is designated as the comparison llip flop for floating point addition and subtraction and division, flip op Nz is designated as the normalization flip ilop for floating point addition, subtraction and multiplication. Primary gates M, m, E, T Jl, and m are also utilized during the floating operations. m is used during addition and subtraction operation. Ml is used during multiplication operation. it@ is used during divide operation. El signilies the second word time of all operations, and M signifies all succeeding Word times.

Further explanation of a computer and its operation may be obtained by reference to Patent No. 3,237,168, issue date February 22, 1966 for Computer invented by me. The various operations and modes of a general purpose, scientific computer are set forth in that application as well as a description of conventional logic not-ation. Logic for fixe-d point operations to which reference is made herein is included in that application. For example, xed point division and multiplication operational logic is described.

FIG, 5 is a further explanation of each of the codes. It is noted that code 23 (FMP, floating multiply) is primarily involved in this description. However, in carrying out this code, other codes are forced (entered). For example, fixed point multiplication mode 63 may be temporari-ly entered to make use of its right shifting capability. AAs soon as the shifting is accomplished, that mode is ended `and others are forced until the floating point operation is completed. Also, the addition .mode 73 may be temporarily entered into. Additional modes described herein are also entered as necessary.

FIGS. ll and 12 illustrate examples of logic mechanization inside a computer for the floating multiply operation. Symbols used for the figures to designate and gates, or gates and flip flops are Well known in the art.

FIG. 13 illustrates an example of logic mechanization using conventional diodes, resistors, and voltage supplies. The C1 flip ilop, which may be constructed as set forth in FIG. 14, is gated by a clock 80. The other flip flops shown are also gated by clock 80. Flip flops Fm, D3, Ka and gate T33 act to set flip flop Cl to its one state. Primary gates M1 and Tl act to set llip flop C1 to its zero state. Flip flop Kc is one set `and zero set by flip ilops Fm, I2, and I1, G1, Kg, 13a, Fa and primary gate T20 respectively. Discussion of and gates and or gates may be found in Digit-al Computer Components and Circuits by R. K. Richards, 1959.

FIG. 14 illustrates an example of a flip llop circuit which is represented by the box symbols in previous tigures. The flip flop C1 illustrated in FIG. 14 shows two transistors 83 and 84, one of which conducts when an input is received at the l input terminal. The other conducts when an input is received at the 0 input terminal provided a clock pulse from clock 80 is also received. If one transistor conducts, the other is shut olf. Therefore, a -12 v. output is provided at terminal 82 or til depending on whether the ilip ilop is in its one state or zero state respectively. F-lip flop circuits are discussed in Transistor Circuit Engineering by R. F. Shea. Although only certain select portions of the logic have been mechanized, the remaining llogic could be mechanized in the same manner as is well known to those skilled in the art.

FLOATING MULTIPLY The following description analyzes and describes more speciiically the floating point multiplication, FMP.

Preliminary mode, InDo phase FIG. 6 sets forth the InDo preliminary mode whichcommences when the operation `code in the D register is 23. Operation code 23 signifies floating point multiply. It is assumed that the multiplier operand is in the A register originally and the multiplicand operand is copied into the B register during this preliminary InDo phase. During this phase flip flop Fm is one set at T41 time of InDo phase. The logic for this setting is set forth in FIG. 6. The logic mechanization is illustrated in FIG. 1l. In order to count word times involved in the floating point operation, a count of 32 is set up initially in the G register lby writing a l into the G20 or G40 `bit positions and a 0 into the G15 or G35 bit positions. The D6 tlip flop is 1 set at T41 time to convert the operation code from floating point multiply to fixed point Amultiply (63) and ilip flop 13a is 1 set to turn on the m primary gate in preparation for multiply.

U1 phase Since the m primary gate is true, the multiplier bits A2 through A32 in the A register are copied into the R1 through R31 bit positions of the R register. By having R41 copy A2 while the R register is likewise shifted right, the A register is cleared by setting A41 to zero at Tl and shifting right. Logic :for these and other cornmands of this phase are shown in FIG. 7.

During the rst word time the fractional contents of the B register are recirculated in order to preserve the multiplicand. The multiplicand recirculation occurs during Tl through T32.

The most signiiicant bit 4of the exponent, the A40 bit, which is the exponent bias, must be inverted at T1 time 'from A40 to A39 and is written into the loop register channel of the A register directly at T1 time by the A39 flip llop.

The addition of exponents occurs next using standard fixed point adder logic. Flip ilop Rl is one set at T32 time and is zero set at T40 time. When R1 is one set the exponent lof the multiplicand, contained in the B register bit positions B33 through B40, is gated into the adder and is added to the exponent of the multiplier contained in the R register, in bit positions R33 through R40. Flip llop D4 previously had been one set at T33 time to convert the operation code from fixed point multiply to fixed point add. The sum of the exponents is Written into the B register from S flip ilop to B40.

At the end of the U1 phase the B register contains the mantissa of the multiplicand and the sum of the exponents. Flip flop Jo is utilized to detect possible overflow and underow of the exponents during exponent addition.

Flip ilop D4 is zero set at T41 time to convert back to the operation code 63 for lixed point multiply thereby causing primary gate m to be true. The algebraic sign of the product is determined and stored. If the sign bits of the multiplier and multiplicand are not equal then C2 flip flop is zero set. This indicates a negative product. If the sign bits are different, flip ilop D2 remains l set.

Ui phase This phase is the same as fixed point multiplication phase except that the size of the fraction is 3l bits. Logic for this phase is illustrated in FIG. 8. The multiplication process consists of successive multiplications of the multiplicand by each digit of the multiplier, a right shifting of the result of each step by one digit, and the addition of the result of each step to the result of the previous step to form a partial product. The addition of the results of the final step to the previous partial product yields the final product. The adder performs the necessary addition in each step of the multiplication computation. Fixed point addition is employed in performing the successive additions comprising the multiplication process. Fixed point addition, subtraction, multiplication, and division as well as other general computer operations are described in detail in Patent No. 3,237,168, issue date February 22, 1966 for Computer invented by me. The partial product is transferred into the A register through flip flop A39 and is shifted right one digit during `successive steps of the multiplication process. The shift is accomplished by transferring the partial product into A39 rather than A40 thus decreasing the A register length by one bit position. Logic used for the sum and carry flip flops in the adder is identical to that used for fixed point addition and subtraction.

At T32 time the D4 ip flop is one set to stop processing of the A register. By one setting the D4 flip flop operation code 73, fixed point addition, is entered into the computer vwhich causes a termination of the multiplication after 32 bit times. One setting of the D4 flip op also causes the cascaded and gate M Q to be true.

To copy the exponents from the B register to the A register beginning at T34 time the least significant bit present in B41 at T34 is copied into the A40 flip flop.

Termination (part of U] phase) The C1 flip iiop is used to check the most significant bit of the product for possible normalizing. If the product is already normalized then it is the last Word time count of multiply, the termination fiip op Kc is one set which terminates the operation and the entire product is forced to zero.

Normalizing phase (NZ) In the case of a product that requires normalizing, the Nz flip flop is one set at T or T40 to set for normalizing.

Logic mechanization is shown in FIG. 9. Operation code 42 for designating a long left shift operation, is set up in the D liip flops at T41 time. The most significant bit of the R register is copied into the least significant bit of the A register.

the B register re-circulated. The sign of the product is determined and stored during the second lword time. The sign is reinserted into the A register after the product of the multiplication and after the sum of the exponents have been determined and re-inserted into the A register. If the fraction portion of either the multiplier or entered multiplicand is zero, the operation is terminated. The exponents are added and copied into the B register. If an exponent overflow or underflow occurs then flip op .To is one set. During the next 31 word times of the floating multiply operation, the actual multiplication of the mantissas or fraction portions is performed. During this time one multiplier bit is multiplied times the multiplicand and the partial product is stored in the A register. The B register is recirculated during this time to preserve the exponent and the multiplicand. Also during this 31 word times the exponent is copied from the B register into the A register so that at the end of the 31 Word times for this portion of the floating multiply operation the exponent and the product obtained by multiplying the contents of the B and R registers is contained in the A register. Multiplication of the fraction operand is carried out by successive serial additions; for example, each bit of the multiplier operand in the R register is checked, if the bit, called a partial multiplier bit, is a one bit then the multiplicand operand is copied into the A register as a partial product. After each successive serial addition the partial multiplier is lost and the multiplier operand is reduced by one bit. By way of illustration, assume that a multiplier operand of 1011 is contained in the R register and a multiplicand operand of 1010 is contained in the B register, the multiplication operation would be executed as indicated on the following chart:

Multiplier (R register) Partial Multiplicand (B register) Partial Product (A register) 1 X 1010 1010 First partial product.

01010 Second partial product.

(Right shifted 1 bit.)

110010 Third partial product.

(Right shifted 1 bit.)

10000010 Final product.

Operation code 42 is then converted into operation code 72, fixed point subtract, in order to subtract one from the exponent. The Nz phase is terminated by one setting the Kc iiip flop.

Zero termination phase (Ul phase) If any one of the factors is zero, the product is zero and termination occurs immediately. A zero test is performed at T32 time and if the most significant bit is zero, Kc is one set which terminates the operation.

SUMMARY The multiplier operand is originally entered into the A register as an exponent and a fraction. During the first word time of the floating multiply operation the multiplicand operand, also having an exponent and a fraction portion, is copied into the B register and a count of 32 is set up in the G register so that the operation Will be terminated after 32 additional word times. Operation code 63 for fixed point multiply is entered into the D register so that the A register shifts multiplier bits into the R register during the second word time of the floating multiply operation. During the second word time of the operation, in addition to the shifting of the multiplier bits from the A to the R register, the A register is cleared and If the multiplier bit is zero as in step 2 above, then zeros are added to the partial product obtained from the first multiplication which is then shifted right to form the second partial product. The partial product of each step of the multiplication operation is stored in the A register. In step 3 the partial multiplier bit is one so the multiplicand operand is added to the partial product previously obtained. After all the steps of the operation are completed the final product shown by step 5 above is contained in the A register. A check is made to determine if the product is normalized and if the product is normalized during the last word time, the operation is terminated. If it is not normalized then an additional one word time must be utilized so that the product can be shifted left. And, of course, foreach left shift, one must be subtracted from the exponent. Then an additional check is made to determine if the product is normalized, if so, the phase is terminated. FIG. 10 illustrates a block diagram of each phase of the floating multiply operation.

Logical equations A computer utilizing the concept of the invention was set forth and described in the patent application previously referred to. Such computer is also set forth in the Compute switch signals:

Halt: Both H and C signals present Compute: H' only Single cycle: H and C signals present Conditions of C2, C3, C4 for input and output:

Electric typewriter keyboard input and output- C4'C3C2 Electric typewriter punch--C4C3 C2 Electric typewriter reader-C4'C3C2 Auxiliary reader and punch-C4C3C2 Option-C4C3C2 Card reader and punch-C4C3C2 Automatic-program Although the invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of this invention being limited only by the terms of the appended claims.

I claim:

1. In an electronic computer, means providing iloating point multiplication of one operand with another in a plurality of computer word times including an initial computer word time, each of said operands having an exponent portion and a fraction portion, said exponent portion indicating a power of 2 by which said fraction portion must be multiplied to obtain the numerical Valve of the operand represented by said exponent and fraction portions, one of said operands being a multiplier and the other of said operands being a multiplicand, said means providing oating point multiplication comprising means for serially by bit multiplying the fraction portion of said multiplicand by the fraction portion of said multiplier, said means providing oating point multi- 

1. IN AN ELECTRONIC COMPUTER, MEANS PROVIDING FLOATING POINT MULTIPLICATION OF ONE OPERAND WITH ANOTHER IN A PLURALITY OF COMPUTER WORD TIMES INCLUDING AN INITIAL COMPUTER WORD TIME, EACH OF SAID OPERANDS HAVING AN EXPONENT PORTION AND A FRACTION PORTION, SAID EXPONENT PORTION INDICATING A POWER OF 2 BY WHICH SAID FRACTION PORTION MUST BE MULTIPLIED TO OBTAIN THE NUMERICAL VALVE OF THE OPERAND REPRESENTED BY SAID EXPONENT AND FRACTION PORTIONS, ONE OF SAID OPERANDS BEING A MULTIPLIER AND THE OTHER OF SAID OPERANDS BEING A MULTIPLICAND, SAID MEANS PROVIDING FLOATING POINT MULTIPLICATION COMPRISING MEANS FOR SERIALLY BY BIT MULTIPLYING THE FRACTION PORTION OF SAID MULTIPLICAND BY THE FRACTION PORTION OF SAID MULTIPLIER, SAID MEANS PROVIDING FLOATING POINT MULTIPLICATION FURTHER COMPRISING MEANS FOR SERIALLY BY BIT ADDING THE EXPONENT PORTIONS OF SAID MULTIPLIER AND SAID MULTIPLICAND DURING AN INITIAL COMPUTER WORD TIME OF THE FLOATING POINT MULTIPLICATION. 